1. Field of the Invention
The present invention relates generally to a technique for fabricating integrated circuits and, more particularly, to a technique for fabricating wordlines in a memory device.
2. Background of the Related Art
This section is intended to introduce the reader to various aspects of art, which may be related to various aspects of the present invention, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Microprocessor-controlled circuits are used in a wide variety of applications throughout the world. Such applications include personal computers, control systems, telephone networks, and a host of other consumer products. A personal computer or control system is made up of various different components that handle different functions for the overall system. By combining these different components, various consumer products and systems are able to meet the specific needs of an end user. As is well known, microprocessors are essentially generic devices that perform specific functions under the control of software programs. These software programs are generally stored in one or more memory devices that are coupled to the microprocessor and/or other peripherals.
The memory devices include many different types of circuits that are typically formed using semiconductor material. These circuits work together to allow the memory device to carry out and control various functions within an electronic device. One type of high-density memory device is a random access memory (RAM) device. The random access memories are complex integrated circuits, which are fabricated using a variety of designs. Despite their complexity, manufacturers typically attempt to design memories that are inexpensive to manufacture, while at the same time maintain high performance and high reliability.
Random access memory devices, such as dynamic random access memory (DRAM) devices and static random access memory (SRAM) devices generally include a number of memory cells arranged in an array of rows and columns. The rows and columns provide signal paths to and from each memory cell in the array. Regardless of whether the device is a DRAM or SRAM, each memory cell generally includes one or more storage devices, such as capacitors, and one or more access devices, such as transistors. The access devices are generally coupled to the rows and columns of the array to provide access to the storage device. As can be appreciated, the rows and columns may also be referred to as wordlines and bitlines.
It may be desirable to fabricate wordlines that have a low resistance, a low stack height, and little or no cross diffusion. Typically, low resistance wordlines are preferred to maximize current flow through the wordlines even at higher frequencies. Wordlines that have high resistances may slow the speed of a semiconductor device. Accordingly, wordlines may be fabricated using highly conductive materials to maintain a relatively low resistance. Wordlines are generally fabricated out of layers of various materials that are patterned to form wordline stacks on a substrate, such as a silicon (Si) substrate. One conventional wordline stack design may include gate oxide, polysilicon, tungsten nitride, and tungsten layers deposited on a silicon (Si) substrate, for example.
Integrated circuits, such as memory devices, which may include wordlines, are typically fabricated on a substrate through any number of manufacturing processes, such as layering, doping, and patterning. Layering generally refers to adding material to the surface of the substrate by a growth process, such as oxidation, or through a deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). Doping generally refers to the process of implanting dopants into the substrate surface or overlying layer and may be used to increase the current carrying capacity of a region of the wafer or overlying layer of material. The doping process may be implemented before a layer is formed, between layers, or even after the layer is formed. Generally, the doping process may be accomplished through an ion implantation process, using boron or other similar dopants, or through thermal diffusion, for example.
Patterning refers to a series of steps that result in the removal of selected portions of layers or underlying substrate material. After removal of the selected portions of the layer(s), via a wet or dry etch process, a pattern is left on the substrate surface. The removal of material allows the structure of the device to be formed by providing holes or windows between layers or by removing unwanted layers. Patterning sets the critical dimensions of the integrated circuit structures being fabricated. Disadvantageously, errors in the patterning and removal process may result in changes and failures in the electrical characteristics in the device.
In addition to the layering, doping and patterning processes described above, heat treating or xe2x80x9cannealingxe2x80x9d is often used to effect certain changes in the properties of the layered materials. The anneal process may be used to improve electrical connections between materials, improve certain performance characteristics, improve reliability, or enhance the yield of a semiconductor device. Typically, the anneal process involves heating the material to a pre-determined temperature and then cooling the material to recrystalize the structure in a more ordered form or to allow impurities to disperse. This heating and cooling of the material may allow the defects that formed in earlier processes to be repaired. During this process, substantial diffusion of the dopants may occur throughout the semiconductor device. With smaller structures being formed in the layered materials, the diffusion of dopants may be undesirable. As can be appreciated, faster heat treatments such as rapid thermal processing (RTP), may be implemented to prevent the diffusion in the anneal process. With RTP, a constant temperature may be uniformly distributed across a patterned material or semiconductor device to allow the layered materials to recrystalize and minimize the diffusion of the dopants. A variety of rapid thermal processes may be used in the process to assist in the formation of the smaller junctions, such as laser annealing, spike annealing, or impulse annealing.
During the fabrication of wordlines, for example, certain reactions may occur between various layers of material. In one exemplary wordline, a WNx layer may be disposed on a layer of polysilicon. At high processing temperatures, the nitrogen from the WNx layer may diffuse into the polysilicon layer thereby forming a barrier layer of SiNx between the WNx layer and the polysilicon layer. Disadvantageously, the SiNx layer may increase the resistance and decrease the conductivity through the wordline.
Further, during subsequent processing steps, a tungsten (W) layer and a nitride layer may be disposed over the WNx layer. Disadvantageously, a crystallized W2N layer may form on top of the SiNx layer due to the diffusion of nitrogen through the tungsten (W) layer and into the WNx layer at high temperatures. The excess nitrogen reacts at high temperatures with the amorphous WNx layer and forms a dense crystallized W2N layer. Disadvantageously, this W2N layer is difficult to etch and thus may cause problems in fabricating the wordlines.
Further, the dense crystallized W2N layer may inhibit the formation of desirable layers, by blocking the diffusion of one material into another. For instance, the W2N layer may disadvantageously prevent the formation of a titanium silicide (TiSix) layer after titanium (Ti) is deposited on the wordline during downstream fabrication. The TiSix layer may be desirable to reduce the resistance through the wordline and increase the ohmic contact between the metal layers and the polysilicon layer. Accordingly, the W2N layer may be disadvantageous, because it may prevent the formation of the TiSix layer.